1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
A related-art semiconductor memory device is described by taking an EEPROM as an example. FIG. 5 is a sectional view for illustrating a concept of a related-art EEPROM that has a general structure as described in Japanese Patent Application Laid-open No. 2004-071077.
A unit cell of the EEPROM includes a memory main body portion 002 and a select gate transistor portion 001 configured to select the memory main body portion 002. In the memory main body portion 002, there is formed an electrode called a floating gate 013 configured to accumulate electric charge. Accumulating electrons in the floating gate 013 puts the memory main body portion 002 into an enhancement mode where a threshold thereof is high, which is regarded as a “1” state, and accumulating holes in the floating gate 013 puts the memory main body portion 002 into a depletion mode where the threshold is low, which is regarded as a “0” state.
Writing of the “1” state involves applying a positive voltage to a select gate 003 and a control gate 015, setting potentials of an n-type select transistor drain region 005, an n-type memory cell source 011, and a p-type semiconductor substrate 006 to GND, and injecting electrons from an n-type tunnel drain region 009 into the floating gate 013 via a tunnel insulating film 010. In the following, writing of the “1” state is described with reference to band diagrams.
FIG. 6A to FIG. 6D are band diagrams taken along the line A-A′ of FIG. 5, and are illustrations of changes in state in writing of the “1” state. The p-type semiconductor substrate 006 is omitted. EF, EC, and EV in FIG. 6A to FIG. 6D are a Fermi level, a lower end of a conduction band, and an upper end of a valence band, respectively. In this case, the floating gate 013 and the control gate 015 are supposed to be formed of n-type polysilicon.
In a memory cell transistor in a state of thermal equilibrium illustrated in FIG. 6A, under a voltage state in the writing of the “1” state described above, specifically, when a potential of the n-type tunnel drain region 009 is set to GND and a potential of the control gate 015 is set positive, the band diagram of FIG. 6B is obtained. As indicated by the arrow in FIG. 6B, electrons 018 are injected from the n-type tunnel drain region 009 into the floating gate 013 via the tunnel insulating film 010 by a Fowler-Nordheim (FN) current mechanism. A potential of the floating gate 013 with the electrons 018 injected thereinto drops (in FIG. 6C, rises) as indicated by the hollow arrow in FIG. 6C. When a potential applied to the tunnel insulating film 010 is weakened and an FN current stops, writing operation of the “1” state is completed.
An EEPROM is a nonvolatile memory that can retain information even after power-off, and thus, is generally required to have the ability to retain the “1” state for tens of years under a state in which the potential of the n-type tunnel drain region 009 and the potential of the control gate 015 are set to GND as illustrated in FIG. 6D. However, as indicated by the hollow arrow in FIG. 6C, the potential of the floating gate 013 drops due to the electrons 018 injected into the floating gate 013, and thus, in a data retention state illustrated in FIG. 6D, an electric field in a direction of leakage of the electrons 018 injected into the floating gate 013 to the n-type tunnel drain region 009 via the tunnel insulating film 010 is applied to the tunnel insulating film 010. In this state, if the tunnel insulating film 010 is thin or deteriorated, unintended electron leakage 020 may occur as illustrated in FIG. 6D, which may result in data retention failure.
Next, the “0” state is considered. The “0” state is written as follows. A positive voltage is applied to the select gate 003 and the n-type select transistor drain region 005, the control gate 015 and the p-type semiconductor substrate 006 are connected to GND, the n-type memory cell transistor source region 011 is set floated, and the electrons 018 are ejected from the floating gate 013 to the n-type tunnel drain region 009 via the tunnel insulating film 010. This is described below with reference to band diagrams.
FIG. 7A to FIG. 7D are band diagrams of writing of the “0” state, taken along the line A-A′ of FIG. 5. Similarly to FIG. 6A to FIG. 6D, the p-type semiconductor substrate 006 is omitted, and EF, EC, and EV are a Fermi level, a lower end of a conduction band, and an upper end of a valence band, respectively. Further, the floating gate 013 and the control gate 015 are supposed to be formed of n-type polysilicon.
In a memory cell transistor in a state of thermal equilibrium illustrated in FIG. 7A, under a voltage state in the writing of the “0” state described above, specifically, when the potential of the control gate 015 is set to GND and the potential of the n-type tunnel drain region 009 is set positive, the band diagram of FIG. 7B is obtained. As indicated by the arrow in FIG. 7B, the electrons 018 are ejected from the floating gate 013 into the n-type tunnel drain region 009 via the tunnel insulating film 010 by the Fowler-Nordheim (FN) current mechanism. A potential of the floating gate 013 with the reduced electrons 018 rises as indicated by the hollow arrow in FIG. 7C. When a potential applied to the tunnel insulating film 010 is weakened and an FN current stops, writing operation of the “0” state is completed.
An EEPROM is a nonvolatile memory that can retain information even after power-off, and thus, is generally required to have the ability to retain the “0” state for tens of years under a state in which the potential of the n-type tunnel drain region 009 and the potential of the control gate 015 are set to GND as illustrated in FIG. 7D. However, as indicated by the hollow arrow in FIG. 7C, the potential of the floating gate 013 rises due to the reduction in electrons 018 in the floating gate 013, and thus, in a data retention state illustrated in FIG. 7D, an electric field in a direction of injection of the electrons 018 into the floating gate 013 from the n-type tunnel drain region 009 via the tunnel insulating film 010 is applied to the tunnel insulating film 010. In this state, if the tunnel insulating film 010 is thin or deteriorated, the unintended electron leakage 020 may occur as illustrated in FIG. 7D, which may result in data retention failure.
As described above, the problem of data retention failure (retention failure) is inherent in a nonvolatile memory. Japanese Patent Application Laid-open No. 11-067940, discloses a method of reducing the retention failure described above. According to the invention, a lowered concentration of impurities in a floating gate in the vicinity of a tunnel insulating film reduces trap sites in the tunnel insulating film, thereby reducing retention failure caused by the trap sites.
However, even if the method disclosed in Japanese Patent Application Laid-open No. 2004-071077 is used, an electric field in a direction of inhibiting retention of electric charge existing in the floating gate 013 is still applied to the tunnel insulating film 010, and a retention failure described with reference to FIG. 6A to FIG. 6D and FIG. 7A to FIG. 7D is not fundamentally improved. Another method of reducing the retention failure is to simply increase a thickness of the tunnel insulating film 010, which does not fundamentally improve the retention failure described with reference to FIG. 6A to FIG. 6D and FIG. 7A to FIG. 7D. Increase in thickness of the tunnel insulating film 010 requires a higher write voltage, and thus, as a result, a problem arises that a chip size increases.
In other words, those improving methods cannot reduce the thickness of the tunnel insulating film 010 while preventing the unintended electron leakage 020 that hinders data retention. It can be said that this prevents the write voltage from being lowered and the chip size from being shrunk to hinder a nonvolatile memory breakthrough.